After the manufacturing of semiconductor memory devices, having memory chips on a wafer is generally completed, various tests are conducted to determine whether or not the circuit devices within each memory chip operate in conformity with a predetermined specification. Multiple test parameters are used in each test to check the electrical characteristics and operations of the chip.
When any one of control circuits within the semiconductor memory chip has a defect a remedial measure for such a defect for the semiconductor memory device may not be possible.
If a portion among the normal memory cells is determined to be in a defective state, then such a portion of memory cells can be replaced with a redundant memory cell so that the semiconductor memory device can operate normally. In other words, to provide the defect relief, a redundancy circuit containing the fuses that are meltable by a high-energy light such as laser etc., is manufactured together with the memory cell and circuit devices of the semiconductor memory device during its manufacturing process.
A semiconductor memory device such as a Static Random Access Memory (SRAM) employs a multiblock structure in which a memory cell array is divided into a plurality of block units to reduce a speed penalty for an access operation. In order to increase repair efficiency in the multiblock structure, as shown in FIG. 1, a redundancy circuit is connected corresponding to every memory cell block.
According to a conventional technique, a configuration of redundancy circuits in the semiconductor memory device having the multiblock structure is shown in FIG. 1. Redundancy circuits 20, 22, 24 and 26 are connected with memory cell blocks 10, 12, 14 and 16, which are divided into the necessary number through lines 2, 4, 6, and 8 individually and correspondingly. In each memory cell block, a plurality of normal memory cells and a plurality of redundant memory cells are disposed appropriately. Thus, if the normal memory cell or cells have a defect in the memory cell block 10, a redundant memory cell or cells within the memory cell block 10 operate instead of the normal memory cell through the defect relief operation of the redundancy circuit 20.
However, the layout structure of the redundancy circuits where each redundancy circuit is connected corresponding to each memory cell block as shown in FIG. 1 increases an occupied area within a chip, which is a limiting factor for a highly integrated and compact memory circuit chip.
With reference to FIG. 2, the causes of increase in the occupied area within the chip in the layout structure of FIG. 1 will be described in detail. FIG. 2A and 2B show a circuit diagram illustrating the configuration of the redundancy circuit referred to in the FIG. 1. The redundancy circuit is composed of a precharge unit 21, a fuse box 22, a pass transistor array 24, a state keeping circuit 26 and a redundancy enable signal generator 28. The precharge unit 21 precharges a drain node of a P-type MOS transistor PM1 by a level of power source in case a signal PRED is applied in a logic high state. The signal PRED is a combined pulse provided from a main pulse generator when a chip enable signal is applied.
The fuse box 22 is typically disposed in a peripheral circuit region within the chip. A block free fuse box 23 within the fuse box 22 is composed of block free fuses F1˜F4 providing a prominent redundancy flexibility. The pass transistor array 24 responds to a block redundancy address B_RA0, B_RA1 and a redundancy address RA0–RA3 so that a potential of the drain node of P-type MOS transistor PM1 becomes a precharge level or an earth level. The state keeping circuit 26 includes a latch L1 that is used to invert a level state and maintain it when the potential of the drain node of the P-type MOS transistor PM1 becomes a high level or a low level. The redundancy enable signal generator 28 receives an output logic level of the state keeping circuit 26 and a chip selection signal CHIP SELECT applied to a semiconductor memory, and generates a NAND response. The generated NAND response becomes a redundancy enable signal RED_EN.
The fuse box 22 composed of the plurality of fuses F1, F2 and F12 and is connected to a row or column control circuit, such as a decoder of semiconductor memory device etc., through the redundancy enable signal generator 28, and the row or column control circuit is connected to the memory cell block.
A fuse programming is obtained by previously opening or blowing a fuse corresponding to an address of a defective memory cell among the fuses F1, F2 and F12 within the fuse box 22. Thereby, only in case an address corresponding to a defect address for a defective memory cell is applied as address bits RA0–RA3 in a normal operation of the memory device, the redundancy signal generator 28 changes the redundancy enable signal RED_EN provided under an inactive state to an active state. Thus, the redundancy memory cell or block is selected in place of the defect memory cell or block by a decoding circuit, to perform the writing/reading operation of data. Hence, the fuse programming is a type of address code cutting technique, to repair the defected memory cell or block, and is an important technique to increase the manufacturing yield in the process of integrated circuit production.
As the described above, the redundancy circuit shown in FIG. 2 is manufactured first, and then, in case there is a defect in a normal memory cell, a fuse related to its address is opened. Then, a redundancy memory cell corresponding to its fuse opening information is driven instead of the defective normal memory cell during reading and writing operations related to the address of the defective memory cell.
However, as described above in context of FIG. 1, the redundancy circuit shown in FIG. 2 is disposed in every memory cell block, and hence, in order to reduce a speed penalty, four redundancy circuits are required in a case like FIG. 1. That is, if the fuse box is disposed independently within each redundancy circuit then the layout area of fuses increases. Further, the precharge unit 21, the pass transistor array 24 and the state keeping circuit 26, which constitute the redundancy circuit, are each independently disposed, thus increasing the occupied area within the chip.
Furthermore, as shown in FIG. 2, the block free fuses F1–F4 disposed correspondingly to each memory cell block are needed in the fuse box 22 of each redundancy circuit, thus the occupied area of the chip also increases and is a limitation for a high-integration in the memory circuit.
In other words, the redundancy circuit disposed corresponding to each memory cell block brings about a problem of increasing the area occupied by the redundancy circuit in the chip.
Therefore, there is a need for a design and layout capable of occupying a smaller area for the fuse box and the redundancy circuit involving the fuse box, in a high-integrated semiconductor memory chip.